RV32I core, custom-0 extension
DOT4, drawn as a machine
One instruction multiplies four pairs of signed bytes and adds the four products. Change the bytes and follow them through each part.
Figure 1. The DOT4 unit
rs1 and rs2 each hold four signed bytes. Lane i is bits [8i+7:8i]. Each lane has its own multiplier. Two adders sum lanes 0 and 1 and lanes 2 and 3, and a third adds the two partial sums. rd gets the result as a signed 32-bit number. In the RTL the whole unit is combinational in the EX stage, so DOT4 takes one cycle like ADD.
Drag the figure to turn it. See-through shows the bits inside. The bit-product array shows which bit pairs are both 1. It is not the synthesized netlist.
Lane bytes
Encoding
dot4 a0, a1, a2 is an R-type instruction in the custom-0 opcode space. GNU as writes it as .insn r 0x0b, 0, 0, a0, a1, a2. Any other funct3 or funct7 under custom-0 traps.
What DOT4 costs
| DOT4 off | DOT4 on | Change | |
|---|---|---|---|
| Logic cells (of 7,680) | 4,767 | 5,671 | +904 (+19%) |
| Fmax, median MHz |
Post-route estimates from nextpnr for iCE40 HX8K CT256, median of 5 route seeds, same core built with DOT4=0 and DOT4=1 by changing only that parameter. The shipped make timing netlist has the same logic but synthesizes slightly differently: 5,539 cells and 36.05 MHz median, the figure the README quotes. Not measured on hardware. Source: reports/ablation.json.
Figure 2. The iCE40-HX8K Breakout Board
The board image runs the core from block RAM. It loops a self-checking program and shows the verdict on eight LEDs. Run self-test plugs in the USB cable, loads the FPGA and plays what the LEDs would show, following rtl/board_top.sv.
LED0 blinks at its real rate. LED1 and the pass counter assume one instruction per cycle, so they run a little fast. Part placement is simplified. The die map in see-through shows how much logic is used, not where.
What the LEDs mean
| LED | PASS | FAIL |
|---|---|---|
| LED0 | Heartbeat. Toggles every 2^23 clock cycles, even during reset. | |
| LED1 | Bit 22 of the retired-instruction count. Stops changing if the core halts. | |
| LED2 | On after the first matching signature | Off |
| LED3 | Off | On, latched until power-off |
| LED4 to LED7 | Bits 13 to 16 of the pass counter, counting up | Cause: LED4 wrong signature, LED5 trap, LED6 watchdog, LED7 retire count |
Only the wrong-signature failure is exercised in simulation (make board-sim). The other fault choices show what their cause bit would light.
Board resources
| Resource | Used | Available | Share |
|---|
Post-route estimate for the full board image: core, 8 KiB program ROM, 4 KiB data RAM, checker and UART. Fmax MHz against a 12 MHz clock. Expected signature 0x5a978549, 1,591 instructions per pass. Source: reports/board.json.