Pick a trace, then step through it one clock cycle at a time. Every position comes from a recorded RTL simulation of this core.
Fig · pipelineFive-stage pipeline machine← → step · space play
Yellow marks what acts this cycle: the closed gate, armed trapdoors, a bypass pipe in use, the drawer being writtenOne cartridge is one instruction; an empty tray is a bubbleEach cycle is one Icarus RTL snapshot from reports/visual-traces.json, taken at a falling edge. Stalls and flushes shown in a cycle take effect at the next rising edge. Cartridge text is decoded from the trace's instruction words; a fetch past the program reads nop, the word tests/tb.sv fills memory with. Bypass pipe lighting is derived from the stage contents and the forwarding rules in rtl/rv32_core.sv lines 102-112, because the trace does not record mux selects.